1. Field of the Invention
The present invention relates to a heat treatment apparatus and a heat treatment method of a semiconductor wafer, and relates more particularly to a heat treatment apparatus and a heat treatment method of a semiconductor wafer that is used in a manufacturing step of a semiconductor device, such as a PEB (Post Exposure Bake) processing step of a resist film of a chemically amplified type and the like.
2. Description of Related Art
In the manufacturing step of a semiconductor device, the photolithography technique for forming a pattern of photo-resist film has become more and more important in order to attain the further hyperfine structure of the semiconductor device.
For example, in a case of a resist film of the chemically amplified type, the heat treatment referred to as the PEB process is carried out before a developing process is carried out after a process for exposing the resist film. This is carried out in order that acid generated in an exposed region is amplified by the heat treatment, thereby obtaining an exposed line width.
FIG. 5 is a diagrammatically configurative view showing a heat treatment apparatus for carrying out the heat treatment such as the above-mentioned PEB process and the like.
A heating plate 100 for heating the semiconductor wafer, for example, on which the resist film of the chemically amplified type is formed and which is exposed to a predetermined pattern, to a predetermined temperature contains therein heaters 101 divided into, for example, seven regions.
A power supply switch 102 through which a temperature can be set is connected to the respective heaters 101. By turning on the switch, the heating plate 100 is heated to a preset temperature (for example, 130° C.).
In order to use the above-mentioned heat treatment apparatus and perform the PEB process on the semiconductor wafer, for example, at the power supply switch 102, the temperature is set at 130° C., and the semiconductor wafer after the exposure is placed on the heating plate 100 heated to the set temperature after the switch is turned on. Then, the heat treatment of a predetermined time period is performed on the semiconductor wafer. The heat treatment period may be, for example, 90 seconds.
Then, after the elapse of this heat treatment period, the semiconductor wafer is cooled for 60 to 90 seconds and cooled to a normal temperature of about 23° C. (refer to a patent document 1) following hereto. At this time, the semiconductor wafer is cooled by moving the semiconductor wafer from the heating plate 100 onto a cooling plate (not shown) that contains therein a water cooled tube.
[Patent Document 1]
Japanese Patent Application Laid Open (JP-A 2001-23893) (Especially, Paragraph Number 0033)
However, when the above-mentioned heat treatment apparatus is used to carry out the PEB process, a tolerance of variation in a line width is previously large, with regard to the line width of the resist film generated as the result of the execution of the PEB process. Thus, the variation in the temperature of the PEB process is not especially considered, which leads to a problem in controllability of the line width within the surface on the semiconductor wafer. In particular, the problem that the above-mentioned conventional heat treatment apparatus can not suppress the variation in the line width becomes severe toward the hyperfine structure on and after the 0.1 μm-generation.
For example, FIG. 6 is a profile of the temperature variations in the PEB process. The vertical axis indicates the values of the temperature variations, and the horizontal axis indicates the process time.
Temperature variations in an initial period of the PEB process between 0 and about 20 seconds are temperature variations when it is heated to a predetermined temperature, and temperature variations on and after 90 seconds are temperature variations when it is cooled from the temperature of the PEB process.
FIGS. 7A to 7C are views in which the temperatures in the PEB process measured at the respective positions of the semiconductor wafer are plotted. FIG. 7A shows a period between 0 and about 20 seconds during which the temperature rises, and FIG. 7B shows a period between about 20 and 90 seconds during which the temperature is stable in the predetermined PEB processing temperatures, and FIG. 7C shows a period of cooling down on and after 90 seconds, respectively.
They are measured from the center of the semiconductor wafer to the outer circumference thereof, and the respective measured points are all plotted. Thus, the profile has the width corresponding to the variation in the temperatures.
For example, the width of the temperature variation in the temperature rising period is 21.2° C., the width of the temperature variation in the over-shooting region immediately after the temperature has risen is 1.56° C., and the width of the temperature variation in the stable temperature period at the end point (90 seconds) in the PEB process is 0.2° C. Also, the width of the temperature variation in the cooling period is greater than that of the temperature rising period.
For example, in the temperature rising period of FIG. 7A, the outer circumference is higher in temperature than the center of the semiconductor wafer, and in the cooling period of FIG. 7C, the center is higher in temperature than the outer circumference of the semiconductor wafer, as a tendency thereof.
As mentioned above, it is understood that the PEB process has the variation in the processing temperatures within the surface on the semiconductor wafer and that the variation is greater in particular in the temperature rising period and the cooling period of the process.
FIG. 8A is a graph showing a line width when the PEB processing temperature is the highest temperature in an isolated pattern having a line width of 70 nm and a line width (CD (Critical Dimension) value) when it is the lowest temperature, which are calculated from a simulation. Under a proper dose amount, the difference between the line widths reaches 6.8 nm.
Also, FIG. 8B is a graph showing a line width when the PEB processing temperature is the highest temperature in a pattern of a line space of a line width of 90 nm and a line width (CD value) when it is the lowest temperature, which are calculated from the simulation. Under the proper dose amount, the difference between the line widths reaches 9.9 nm.
As mentioned above, in the PEB process based on a conventional method, the variation in the PEB processing temperatures within the surface on the semiconductor wafer is severe. Thus, it is desired to carry out the heat treatment while suppressing the variation.
Also, suppressing of the variation is required not only in the PEB process. For example, even for another heat treatment to be performed on the resist film, such as a pre-baking process for evaporating solvent in the resist film after the formation of the resist film and the like, or the heat treatment using a heating plate which is performed on the semiconductor wafer, it is similarly desired to carry out the heat treatment while suppressing the variation in them within the surface on the semiconductor wafer.
The present invention is accomplished in view of the above-mentioned problems. Accordingly, there has been a need to provide a heat treatment apparatus and a heat treatment method of a semiconductor wafer, which can carry out a heat treatment so as to suppress variations in line widths within a surface on a semiconductor wafer and the like.